Scaled graphic line display on cathode-ray tube with uniform brightness

ABSTRACT

In a radar PPI display system, uniform brightness is maintained for graphic lines displayed between radar sweeps by generating every graphic line at the same rate regardless of range scale selected. Range data for each graphic line is scaled as a function of range scale in a range counter which counts down clock pulses at a fixed rate, thus scaling each graphic line as a function of range scale.

United States Patent [191 Dalena et al.

[75] Inventors: Rudolph Dalena, Placentia, Califi; Donald F. Walker, Boulder, Colo.

[73] Assignee: Hughes Aircraft Company, Culver City, Calif.

[22] Filed: July 24, 1972 [21] Appl. No.: 274,548

[52] US. Cl. 315/18 [51] Int. Cl. HOlj 29/72 [58] Field of Search 343/5 DP, 5 R; 315/18 [56] References Cited UNITED STATES PATENTS 3,582,705 6/l97l Waller et al. 3l5/l8 Timin Gra hic- Operulor c 1 9 Control 1451 Feb. 12,1974

3,721,856 3/l973 Dick 315/18 X 3,683,380 8/1972 Cantwell, Jr. et al. 343/5 DP X 3,500,402 3/1970 Huele et al. 343/5 DP 3,723,803 3/1973 Harrison et al..... 315/18 X 3,718,832 2/1973 Premru et al. 3 l5/l8 Primary Examiner--Malcolm F. Hubler Attorney, Agent, or Firm-Martin E. Gerry [57] ABSTRACT 5 Claims, 7 Drawing Figures Control panel Start Count Range Gmpm L e Le th Line l7 Azimuth X Channel 14 D/A Converter H Radar Antenna k Deflection Amphf'er 9 Azlmuth Signal Ready Control Processor Unit Y Channel 3 WA Converter Video ger e Amplifier Pulses Llo LIE R a. d a r Transmitter And Receiver Video [mensiv Processed contra! Video Um 'PM'IENTED I I I 3.792.304

SHEET 3 BF 7 Fig. 3

Y off- Screen Bits X Offset State X off Screen Bits Store D010 1 Sin I I' I X Count X I Accelermed X Drm. Reg. Direction SIope I Count I(Sign) Counter Controt Kl L34 I I 3? I A! use i X I x L I Pulses Km Range v Drm I I (Line Length) I I I L32 I Y Offset ISTGTG I Data Start Coumer Range I Count Control x Coumer I I Y I 3D I Slope I P99" 41 use I I -39 t ICount Clock 7 Y I K I Drm I C III I 36 Temporary I I Storage EI Qi I Register I C l 357 I I Y Count I Y Drm Reg Direction (Sign) 24 Cos Store mu u m 7 Fig. 4.

Clock off Screen Normal C lock Enable Normal Clock Fast Clock Zero Detector Rescole Reset PATENIEBFEB I 2 1974 State 1 Ron e Re isferto Counfer Transfer Load Range PAIENTEB FEB 1 2:914

WEI 5 BF 7 E PEM 8:500 wmcom mma IN \mmkm mmmmmmml 203mm 22:5

:05 52am to 0 95% v I! 02% 620 2 k 8 22m SCALED GRAPHIC LINE DISPLAY ON CATI-IODE-RAY TUBE WITH UNIFORM BRIGI-ITNESS The invention herein described was made in the course of or under a contract or sub-contract thereunder with the Air Force.

BACKGROUND OF THE INVENTION This invention relates to cathode-ray-tube (CRT) displays, and more particularly to display of graphic lines.

Real-time radar systems have a variety of data to display. For example, in a plan-position-indicator (PPI) system, it is often desirable to display an antenna reference azimuth with respect'to the radar. That azimuth can be displayed during the radar dead time, i.e., during the time after the radar system stops listening for return signals and before another pulse of. energy is transmitted from the antenna. Following the dead time, the radar system displays the usual radar return signals.

It is desirable to have each graphic line displayed with the same brightness for all display range scales. Normally, a different range scale requires a different CRT deflection rate. To retain the same brightness, it has been the practice to switch an intensity compensation circuit as a function of range scale, or to otherwise vary intensity as a function of the rate at which the CRT beam is being deflected. This has not been completely satisfactory because constant brightness between range scales is difficult to maintain with intensity compensation techniques. Since the characteristics of the CRT differ from one type to another, due to the different materials used on the fluorescent screen, it is necessary to design the compensation circuit for the particular type of CRT. In each case, the design is difficult to achieve because of nonlinearities in the characteristic of the tube.

OBJECTS AND SUMMARY OF THE INVENTION An object of this invention is to obviate the need for intensity compensation circuits in a CRT display system and still assure a display of graphic lines with uniform brightness for all range scales.

This and other objects of the invention are achieved in a cathode-ray tube (CRT) display system using digital X- and Y-axis deflection systems for all line graphics, and having a variable display scale for all line graphics, by providing the same constant deflection rate for the CRT beam for all range scales. A lengthcounting means-stores a desired line-length number in binary form. Upon. receipt of a start command, pulses from a constant clock source are counted. When the number of clock pulses counted is equal to the stored line-length number, preferably determined by counting the stored number down to zero, the line end point is reached. A digital rate multiplying means stores lineangle data in the form of digital values of cosine 0 and sine 0, and multiplies the line length count by the stored cosine and sine values to obtain X and Y trains of pulses. Slope counting means count up, or down,

V 2 the line-length data is scaled by shifting it to the left (in the direction of the most significant bit position) n bit positions as entered into the length counting means. As the line-length number is shifted left for range scaling, an extra bit of resolution is added per range scale to maintain accuracy in the line end point.

The novel features that are considered characteristic of this invention are set-forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates in a block diagram an exemplary environment for the present invention;

FIG. 2 illustrates in a block diagram a general implementation of the deflection unit of FIG. 1;

FIG. 3 illustrates in a block diagram a preferred embodiment of the line generator unit of FIG. 2 in accordance with the present invention;

' FIG. 4 illustrates an exemplary embodiment of the range counter and temporary storage register in the line generator unit of FIG. 3;

FIGS. 5 and 7 are timing diagrams useful in understanding the operation of the line generator unit of FIG. 3; and

FIG. 6 is a logic diagram of an exemplary digital rate multiplier for the line generator unit of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, which shows a general block diagram of an exemplary radar system, the present invention relates to the novel manner in which a deflection unit 10 is implemented for generating graphic lines on the face of a cathode-ray tube 11 during radar dead time. A radar transmitter and receiver 12 transmits pulses through an antenna 13 at a fixed rate controlled by trigger pulses from a radar signal processor 14, and after each pulse listens for a return signal for a specified period. The same antenna is used for both transmitting and receiving radar pulses.

The pulse repetition frequency (PRF) is selected to allow for more than enough time for returns from the maximum range of interest. The radar signal processor 14 generates a trigger each time a radar pulse is to be transmitted and transmits the trigger pulse to the deflection unit and graphic control unit 15 for timing a period, the listening period during which video pulses are received and processed for display. The processor receives the video pulses and, through the deflection unit and a video control unit 20, controls their display in the usual manner, such as in a plan position indicator (PPI) mode. Following the listening period, a START pulse is transmitted by the graphic control unit 15 to the deflection unit to initiate and maintain an alternate mode of controlling the CRT beam for graphic-line display.

For the PPI mode, the necessary control inputs are provided by the radar signal processor. For graphic-line mode, the necessary control inputs are manually provided by an operator control panel 16. In each mode, the deflection unit outputs are X and Y coordinate values for the CRT in digital form. Two units 17 and 18 convert the respective X and Y coordinates to analog form, and amplify the analog signals to the level necessary for a deflection yoke 19 of the CRT. The video control unit 20 blanks the CRT beam while the transition from one mode to the other takes place, and as otherwise required during both the normal PPI mode and the graphic-line mode.

Before proceeding with a description of a preferred embodiment of the invention, a more detailed description of the organization and function of the deflection unit will be given with reference to FIG. 2. A clock generator 27 provides a stable frequency reference for sweep and system clocks. A 20.7205 MHz crystal controlled oscillator is used to generate a clock pulse train which clocks an eight bit sweep clock counter and a five bit system clock counter. Sweep clocks are generated during radar display time, and therefore not of interest in the present invention which is active only during radar dead time. The system clocks at 647.515 KHz are generated by the five bit counter from the 20.7205 MHz clock. From the system clock counter, the following clocks are derived: 10.36 MHz for graphic line fast count; 5.18 MHz for normal graphic line count; and 647.515 KHz for use in all units as a basic clock.

An azimuth control unit 22 receives in digital form antenna azimuth from a line receiver 23 or a graphic line azimuth 0 from the graphic control unit (FIG. 1), and converts the received azimuth value to sine 6 and cosine 6 values (in digital form) for use by X and Y digital rate multipliers in a line generator unit 24. Count direction is also included in the converted azimuth value as a sign bit for use in an X and Y axis control unit 25.

The azimuth control unit 22 consists ofa storage register for the azimuth value to be converted and a readonly memory which uses the azimuth value to address a look-up table and read out the sine and cosine values. It also includes a network to decode the azimuth value and provide the proper signs for use as X and Y axis count direction control.

Loading of the storage register is controlled by the graphic control unit during the initial part of radar dead time, i.e., immediately after the radar ranging period is concluded. The azimuth value thus stored is retained throughout most of radar dead time. Near the end of that time, the radar antenna azimuth is loaded into the register for use during radar sweep time. A READY signal is also transmitted to the line receiver to signify that valid antenna azimuth is available at its inputs for sampling.

What has been described with reference to FIGS. 1 and 2 is the environment of the present invention in general terms. Other equivalent environments may use the present invention to equal advantage. The line generator unit 24, which embodies the invention, will now be described with reference to FIG. 3.

The line generator unit 24 is comprised of four basic parts: the range counter and counter control 31; the X and Ydigital rate multipliers (DRM), 32 and 33, and associated X and Y DRM registers, 34 and 35; a temporary storage register 36 and accelerated count control 37. The last two are used only for off-screen line control generation, as will be more'fully described with reference to FIGS. 4 to 6. During radar dead time, the range counter stores graphic-line range data from the graphic control unit and, upon receipt of a START COUNT command from graphic control unit, counts down until an all-zero state is reached. The range counter count down to zero determines that the line end point has been reached and terminates the generation of the line. The unit then awaits receipt of the next line data and start command.

Each time the range counter is loaded, the range data is also rescaled with LSBs stored in the temporary storage register 36 for use in the event an off-screen condition is present. That condition may be present when X and Y slope counters 38 and 39 are loaded with X and Y offset data from the graphic control unit corresponding to a starting point for the line to be generated off the screen by a predetermined amount.

The line is generated at a constant rate for a constant brightness by generating the X and Y trains at a fixed rate as follows. The registers 34 and 35 store the line azimuth (angle) data in the digital form of sin 0 and cos 6, respectively, as noted hereinbefore. While the range counter is counting down, at a predetermined constant rate, the X and Y DRMs receive the outputs of the range counter, the count clocks at 5.18 MHz, and the azimuth sine and cosine data. The DRMs transmit the count clock as a multiplication function of X=R sin 0 and Y=R cos 0 in a well known manner. When the range counter has reached zero, the X and Y pulse trains stop, thus having produced a number of X and Y pulses proportional to R sin 6 and R cos 0. The slope counters 38 and 39 count the respective X and Y pulses to generate in digital form the deflection values necessary for the CRT beam to trace the desired line. These digital values are continually being converted by D/A converters in units 17 and 18 (FIG. 1) for use in the CRT deflection units.

Prior to the START COUNT command, initial X and Y line position values are stored in the X and Y slope counters. The counters then count up or down as directed by count direction control signals from the azimuth control unit according to the signs of the sine and cosine values entered into the registers 34 and 35. For an angle 0 in the first quadrant (0 to 90) both count up; in the second quadrant (90 to l), the Y slope counter counts down; in the third quadrant (l80 to 270), both count down; and in the fourth quadrant (270 to 360), the X slope counter counts down. In each case, the count is at the rate of the respective X and Y pulse trains. That rate is determined by the rate at which the range counter receives count clock pulses from the azimuth control unit. That rate is a predetermined constant rate; therefore, the line is generated at a constant rate.

When the range scale is changed, that line generating rate is maintained constant by rescaling the range data in the range counter as a function of range scale. The range value entered is shifted to the maximum right data position (LSBs) for the maximum range, Range 1 in the following table. Each range scale decrement results in a range data left shift of one position as shown in the following table. The range counter data is indicated by X s which are to be interpreted as representing binary 0 and 1 digits.

Wm- TAB Lif M L Maximum 1% Range counter I? count qovtl in I3 00 S 0ooooo0XXXXXXXXX 511 OOOOOOXXXXXXXXXX 1023 OOOOOXXXXXXXXXXX 2047 OOOOXXXXXXXXXXXX 4095 Range1/1fi OOOXXXXXXXXXXXXX 8191 Bengal/32.... OOXXXXXXXXXXXXXX 16383 Bengal/64.-" o X X X X X X X X X X X X X X X 32767 Rangel/IZB -XXXXXXXXXXXXXXXX 65535 As range data is shifted le ftfan emJEFJEs'dEtBH it, I SCREEN signal is being generated by the axis control is added per range scale to maintain line end point acunit 25. All of the required clocks are being continually curacyv Since the number of clocks required to count generated from the high frequency clock of 20.7205 down the range counter to zero is doubled per range hgHz so thlt selection is merely a matter of getting out sca e decrement, this effectively doubles the line t e desire count cloc length, but the deflection rate of the CRT beam is not The OFF SCREEN signal is developed in the axis doubled. The LSBs of the slope counters always toggle control unit as indicated in FIG. 2, as well it may be, by at the same clock rate resulting in a constant generating m n t ring the X OFF SCREEN bits and the Y OFF rate for lines at all range scales. In the past, the range SCREEN bits, -g-, the bit Positions 9 through 15 0f e counter always counted down the maximum number of X and Y SiOPe Counters, Where the h Positions are clocks required for the minimum range scale (in the e h from the If the Sum of blts 9 through case shown 65535 clock pulses) regardless of range m elther Slope counter q R, where the 15 scale selection. The line length was doubled by delet- We t hete e et eeteeh thing one LSB from each slope counter per range scale .Ohee'the F SCREEN e g generated, p y decrement. That technique resulted in the line generablanking eeeuhs y means the Video Control unit tion rate being twice as fast per range scale decrement t fast eohht ehahted'te oeeur ht the graphic mode i the dock rate constant until the off-screen condition IS no longer present.

The range counter receives count clocks from the The Slope eeuhtets eehtd beglhftt a P h greater, clock generator 27 (FIG. 2). The clock generator than 1.5R In either axis (where R is the radius of the lects for the count clocks an appropriate sweep clock 30 g y g h the te i h count l a P h wilthth rate during radar sweep time, i.e., during radar live 0t axeeatw 1e thhe hettha eehhhhgts time. Those sweep clocks are selected as a function of Shthedrange scale. For the graphic line mode, i.e., during Ahexemptaty hhptethehtaheh of the e e counter radar dead time, the count clock rate selected is always z fl fi greater h g Wtth e 5.18 MHz, unless the origin of a graphic line is detereheete e counter 15 comprise of 16 hmary mined to be greater than,for example, 1.5 times the se-- Stages 1 t0 16 Whleh Operate h lected range radius, in which case a 10.36 MHz clock .ceuht dowh mode as f Sweep range eehhtet E h is selected for the count clocks to provide a fast count P mode) f as a range counter p e until the line is within the LS-times criterion. Then 40 l Assoelated With the stages Q to 0, are 19 b1- the slower 5.18 MHZ clock is substituted for display of y stages 21 to Qss g 9 as a range buffer the line generated at a constant-rate on the screen. If tegtstet, h Prevtde t e hheheh of t e temporary the line generated goes off the screen near its terminal Storage reglstet end, that condition is detected by a slope count in exe velue entered h rahge h t e a cess of 1.5 times the selected range radius and the line h e hhe from the gtephte cohttet uhtt Settahy count is terminated in any suitable manner, as by reset shtfted thto the buffet regtster stages Q24 to Q89 under ting the range counter to zero at that point via the ac- State 1 of the counter Control The range Value celerated count control unit 37. In that manner, a fast t tehge Seated dht'lhgstate 2 e the eohttotseahhg count is produced to complete the line-generation proearned out as a ttthettoh 9 p yf Selection cess in a shorter period of time than would otherwise h fast eohht deteetloh- T Seahhg normally beg the c489, hum, A H fled t a e ys (X g fi a a M al y To accomplish thisgraphic lme display, the line gen 0) TABLE 11 i 3 "s'sneamgavme' Maximum 9 4 count down 0ooo0ooXXXXXXXXX 511 oo00ooXXXXXXXXXX 102a OOOOOXXXXXXXXXXX 2047 OOOOXXXXXXXXXXXX 4095 OOOXXXXXXXXXXXXX 8191 OOXXXXXXXXXXXXXX 16383 OXXXXXXXXXXXXXXX 32767 cration unit 24 (FIG. '2 responds to the START LINE signal to switch the count clocks from the clock generator 27 from a sweep clock selected for the range being used for normal PPI display to a clock at 10.36 MHz or 5.18 MHz, depending upon whether or not an OFF If the offset position initially loaded into the slope counters is detected to be at a point greater than 1.5 times the selected range radius in either the X or the Y axis, for 32, 16 or 8 mile selections, the register is additionally range scaled as follows:

TABLE III Additionally scaled range value Temporary Q t% storage Range select 3 4 Q23 Q22 Q21 32 OOOOOOXXXXXXXXXXXXX 1s ..OOOOOXXXXXXXXXXXXXX s ..OOOOXXXXXXXXXXXXXXX A gate 41 is enabled by the State 1 signal for serially dius and A is equal to 2"/X, and where n is the accelerloading the range value. Gate 42 is not used during 10 ated count multiple, such as 2, 3, 4, etc. (chosen to be graphic-line display, and gate 43 merely ORs the out- 3 in this illustrative embodiment) and X is the number put from these two load control gates. The State 2 Sigof resolution elements per display radius. Recall that nal then enables the shift operation to take place. A upon detecting an off-screen condition due to initial PRESET signal from the control 31 is set true after the offset in the X and Y slope counters, the range value maximum period required for shifting, i.e., after range normally loaded into the range counter (Q 0, via scaling is complete. That enables the scaled data to be the normal register stages (Q Q is shifted down entered in paral el into Stage O1 o Q16 from Stages Q24 three bit positions such that the three LSBs of the t0 Q39- range value are shifted down into temporary storage If an off-screen condition has resulted in the shift of (Q Q The result is a scaling of the range value data bits into the temporary storage register positions h h t, except f h three LSB i temporary Stor- 23 22 and 21 the three least Significant bits of the age, the actual range value is literally being counted range Value are not entered into stages r to 3 d down at 8 times the normal rate per clock applied. In most significant bit of the range value is entered three addition clock rate has been d ubl d lth h Stages down into Stage l3- T results in Counting that is not necessary and is incidental to the present indOWfl e g times less Clock PulseS than normal While 25 vention, but is done when the circuits used are capable the slope counters are counting up or down to within f operating at frequencies greater th th normal 1.5 R. The deflection counters are caused to count l k rate f 5 18 MH I h t manner h slope eight times the normal y g g in pulses to be Counted counters will receive X and Y pulses at rates increased from Stage Q1 t0 the fourth least Significant bit of the by a factor of 2 due to the doubling of the clock rate. slope counters during fast count down, i.e., during the To compensate f r the fa t that the range value has presence of an OFF-SCREEN signal. This is schematically illustrated in FIG. 3 by a relay K, which is energized by the accelerated count control unit 37 to switch contacts K and K from the LSE position of the slope counter to the fourth LSB position. In practice, electronic gates would be used instead of the relay to switch the X and Y pulses to the fourth LSB.

The range counter count down is enabled by the START COUNT control signal at State 4 of the counter control 31. A timing diagram for that control unit is shown in FIG. 5. The range counter counts down at the normal count rate (5.18 MHz) to zero, assuming no off-screen condition is present. At that time, an END LINE signal is sent to the graphic control unit 15 to signify that the line count for the commanded count is complete. That END LINE condition is determined by detecting a zero in all stages O to Q of the range counter. The counter control may thus consist of simply a flip-flop set by a START COUNT signal and reset by the END LINE signal.

When a zero is detected in the counter, the control flip-flop is reset. in practice, however, the counter control may be comprised of a more complex network to accommodate more functions, including range sweep during radar live-time not involved in this invention. It may also include a logic network for controlling the scaling described with reference to FIG. 4.

If an off-screen condition is detected, the range counter receives the fast count clocks (10.18 MHz) until both X and Y deflection counters count to within 1.5 times the range radius area, as noted hereinbefore. For example, if the range scale selected is 8 miles, the fast count is continued until the X and Y slope counters are each at or within 12 miles deflection for the scale of R=8 miles. Stated in general terms, fast count is continued until the slope counters are within R AR with reference to the CRT center, where R is the display rabeen additionally scaled by shifting down three places, the slope counters are effectively shifted down three places by switching the X and Y pulse trains from the LSBs up to the 4th LSB, i.e., to stages corresponding to stage Q 4 of the range counter as noted hereinbefore by energizing the relay K or the equivalent in electronic gates. This switching is done in response to the OFF SCREEN signal within axis control unit 25. In that manner, the range counter effectively counts down 16 times faster than normal, and the slope counters likewise count up, or down, 16 times faster than normal.

Once the fast count mode is initiated in response to an OFF SCREEN signal, the range counter counts down at the fast clock rate (10.18 MHZ) until both X and Y slope counters are within 1.5 times the range ra dius, as noted hereinbefore. At this time the OFF SCREEN signal is low and the remaining range value is rescaled up three bit positions. At the same time, the three least significant bit positions in temporary storage are brought back into play to restore the endpoint accuracy of the original graphic line specified. Thereafter, the count down of range value continues at the normal clock rate (5.18 MHZ) while the X and Y pulse trains are redirected to the LSB's of the slope counters by de-energizing the relay K or the equivalent in elec tronic gates. Offset stored in the 3 LSBs of the X and Y slope counters are also maintained stored for line end point accuracy.

To accomplish this rescaling, the content of the range counter (stages 0 Q is transferred in parallel to corresponding stages (Q Q of the range shift register in response to a RESCALE INITIATE pulse gen erated by the accelerated count control unit 37, as shown by the timing diagram of FIG. 5. At the same time, the content of the temporary register (Q Q is transferred in parallel up three bit positions into stages Q Q of the input register.

9 Following the RESCALE INITIATE pulse, a RESET RANGE COUNTER pulse is transmitted by the accelerated count control unit to reset counter stages Q Q Next in sequence, a REGISTER-TO-COUNTER pulse from that control unit transfers the content of the register (Q Q to the counter stages (Q, Q Once this is done, a NORMAL CLOCK ENABLE signal is initiated by the control unit to permit the normal clock (5.18 MHz) to drive the range counter until count zero is achieved to generate the END LINE signal shown in FIG. 5.

The selection of the fast clock of 10.36 MHZ during the presence of an OFF SCREEN signal and the normal clock of 5.18 MHz during the presence of a NORMAL CLOCK ENABLE signal is accomplished by gating, i.e., by implementation of the logic COUNT CLOCK (FAST CLOCK) (OFF SCREEN) (NORMAL CLOCK) (NORMAL CLOCK ENABLE) as indicated by a logic network 45 in FIG. 4. The NORMAL CLOCK ENABLE is generated initially upon the START command being generated unless the OFF SCREEN signal is true at that time, in which case the fast count sequence ensues. In either case, once the normal count is started, the END LINE signal is generated when the range counter reaches zero or when a count from on to off-screen is subsequently detected. This may be accomplished by anding the NORMAL CLOCK ENABLE signal with-a COUNTER ZERO signal in one gate and the NORMAL CLOCK ENABLE with the OFF SCREEN signal, and oring" the outputs of the two gates to generate the END LINE signal. In that way a line started on the CRT screen is terminated when either the X or the Y slope counter reaches 1.5

R, such as when the line is started off center and/or when the range scale places the end point of the line off the screen. If the end point is reached before an off screen condition can occur, again due to an offset or a range scale selection, the line generating process is terminated. A decoder 46 is shown in FIG. 4 for detecting the count of zero in the range counter. A logic network 47 is connected to that detector to produce the END LINE signal as just described. It is, of course, to be understood that the video control unit 20 blanks the CRT beam whenever the beam is off the display screen in the usual manner.

The digital rate multipliers (DRMs) 32 and 33 derive their inputs from the range counter 30, just described with reference to FIG. 4, and the read-only memory in the azimuth control unit 22 (FIG. 2). The latter provides sine and cosine functions for the angle 6. These functions are stored in the X and Y DRMs according to the following table:

TABLE IV OUADRANT X DRM Y DRM 1 (-90") +sine0 +cosine0 II (90l80) +sine0 cosine0 lll (l80-270) sine0 cosine0 lV (270360) sine0 +cosine6 The X DRM gatesmeraiEEounters $B (61) Zridj LSB (Q etc. sine 0 value MSB, 2nd MSB, etc. (and a count clock for synchronization) such that the X pulse train contains pulses at the rate R sin 0. Similarly, the cosine DRM gates the range counter LSB (Q,) 2nd LSB (0 etc. with the digital cosine 6 value MSB, 2nd MSB, etc (and a count clock for synchronization such that the Y pulse train contains pulses at the rate R cos 0) The signs of the sine and cosine function control the up (for positive) and down (for negative) count operation of the X and Y slope counters.

Various techniques are known for implementating these DRMs but a preferred implementation is shown in FIG. 6. The 8-bit sine, or cosine value, is stored in a register 50 in response to a LOAD pulse produced by the azimuth control unit 22 (FIG. 2). The binary digits A through H (LSB through MSB) are stored in the respective 8 stages Q, to Q A bank of NAND gates 5] enable NAND gates 52 to 55 through NAND gates 56 to 57 to transmit DRM CLOCKS as the range counter toggles. In that manner the DRM ands the range counter LSBs with the sine, or cosine, digits and the BASIC CLOCK such that the PULSE TRAIN at the output enables the slope counter to which connected to count at the rate R sin 0 or R cos 0. The MSB output Q of the register 50 enables 50 percent of the BASIC CLOCKS for outputs when true (equals to 1). The next MSB output Q4 enables 25 percent, and so forth, each lower MSB enabling half that of the last in the sequence, to the LSB output Q43 which enables 0.390625 percent of the total BASIC CLOCKS for outputs. The error at 45, 135, 225, and 315 is calculated to be only 0.316 for the eight-bit DRM. At the cardinal (axis cross-over) points, less than percent of the BASIC CLOCKS are transmitted, resulting in a very small range error, but no azimuth error since the DRM output for the complementary output is zero.

It has been assumed that the graphic control unit 15 (FIG. 1) provides the timing for the control of graphic line display in this exemplary embodiment. However, in practice other functions are to be performed by the display system which are not here involved. Accordingly, in any given radar display system embodying the invention, a separate and more complex timing control would be provided by a separate unit. In each case, the timing would be within a predetermined time frame which includes the control signals that have been referred to hereinbefore. I

A typical time frame employs a 3-stage binary counter which cycles through eight distinct states 0, 1, 2, 7. The different states are decoded to time the different events. FIG. 7 shows such a typical time frame from the end of a state 0 used for radar sweep through states 1, 2, 3 and 4. The first three states 1, 2 and 3 are used to prepare the system for graphic display.

Each of the states I, 2 and 3 is timed in sequence by a 4-bit binary counter which counts 16 basic clock pulses for each of those states. State 4 then runs an indefinite period as required forthe graphic line to be displayed, i.e., until an END LINE signal is generated to advance the sequence counter tostate 5.

The remaining states 5, 6 and 7 are used in a manner similar to states 1, 2 and 3, but to prepare the system for radar sweep display. Then the radar sweep period 0 is initiated. Since those states (5 through 7 and 0) are not involved in this invention, only the timing sequence for states 1 through 4 are discused with reference to FIG. 7.

During state 1, which gates data through NAND gate 41 (FIG. 4), the SHIFT ENABLE signal is true. This allows a range count to be shifted into register stages Q through Q At the same time, the slope counters 38 and 39 are enabled to store X and Y offset values. Following that, during state 2, the range count is scaled, and in the event of an off-screen condition, the

range count is further scaled to shift the three least significant digits into temporary storage register as described with reference to FIG. 4. A LOAD RANGE signal is then transmitted through NAND gate 48 to transfer the contents of stages Q through Q in the register to stages Q through Q in the counter. The OFF SCREEN signal, which requires the further scaling of range count prior to loading it into the counter, is not a timing signal and is therefore not shown in FIG. 7. Its role in initiating an end-of-line sequence is more clearly shown in FIG. which shows the pertinent portion of state 4 in larger scale.

During the first part of state 1, an ENTER LINE AZI- MUTH signal is generated to enable the azimuth control unit to store the azimuth of the graphic line to be displayed. Then during clocks 8 and 9 of state 2, the sine and cosine values of the line azimuth are stored in the X and Y DRM register. The graphic display system is then ready to start, a r1d a START COUNT signal is generated during clock 4 of state 4.

The scale selection is made by the operator at the control panel 16, and through the timing control unit provides the SHIFT ENABLE signal for the l6 clock perio ds duringstate l plus one additional clock period during state 2 for each range increment from 8i to 16 miles, from 16 to 32 and so forth. For example, if a range of 128 miles is selected, the SHIFT ENABLE signal is extended for four more clock periods. The SHIFT ENABLE signal is then turned off and after the seventh clock period, i.e., after maximum range scaling 30 has been permitted, it is turned on again for three additional lock periods if an off-screen condition is present to provide additional scaling as described hereinbefore with reference to Table III. In that manner the SHIFT ENABLE is used to provide scaling of range and to provide additional scaling for the fast count mode. Once the START COUNT signal occurs, the OFF SCREEN signal will select the fast clock. If such a fast clock were not provided, the normal clock would be used, and fast count still provided by this additional scaling, as noted 40 hereinbefore.

If the off-screen condition is still present when the range counter has counted down to zero during a fast count, the sequence of displaying the graphic line is terminated. Otherwise, the sequence of FIG. 5 is followed to rescale the range count for normal operation. Once counting has started at the normal rate, for on-screen display of a line, the counting will continue at the normal rate until the end of the line is reached, even if the end is off the screen. This is because for a PPI display 50 it is normally not expected that a line will go from onscreen to off-screen. In other applications, such as for mapping, that may occur frequently, and if so, it would be an obvious expedient to use the present invention by interrupting the count and reiterating the sequencing cycle from state 2 clock 7, through state 4. The current state of the range counter would simply by regarded as the range scaled input of the line length and additionally scaled for a fast count until the end of the line is reached.

Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art. It is therefor intended that the claims be interpreted to cover such modifications and variations.

What is claimed is:

1. In a cathode-ray tube display system having digital means for deflection of an electron beam in said tube,

said digital deflection means including means for storing a number proportional to the length of a graphic line to be displayed and means for counting a number of fixed-frequency clock pulses equal to said stored number to control said deflection means in displaying a graphic line, an improvement comprised of means for scaling said stored number for a desired graphic display scale by shifting said stored number in said storage means, thereby altering the number of clock pulses counted for the graphic line displayed to alter the scale thereof while maintaining the deflection rate of said beam constant for all range scales, thereby maintaining uniform brightness in the display of graphic lines of all lengths at all scales.

2. In a cathode-ray tube display system for displaying graphic lines, said system having digital means for deflection of an electron beam in said tube in an X axis direction and digital means for simultaneous deflection of said electron beam in a Y axis direction while displaying a graphic line ofa specified length at a specified angle with respect to one of said axes, said xand y-axis deflection means including a source of clock pulses occurring at a fixed rate and means for counting a number of said clock pulses proportional to the specified length of a graphic line to be displayed in order to produce a running line length count for the graphic line specified, an improvement comprised of means for storing said length of a line to be displayed in binary digital form, and means for scaling said length for a desired graphic display scale before counting clock pulses by shifting said length in said storing means, thus altering the number of clock pulses counted to alter the scaled length of the graphic line displayed while maintaining the deflection rate of said beam constant for uniform brightness.

3. Apparatus as defined in claim 2 wherein said scaling means is comprised of a shift register and said scaling means is comprised of means for applying shift pulses to said shift register, one shift pulse for each binary order of difference in the desired scale over a range scale which requires the maximum number of clock pulses to be counted for a line of maximum length.

4. Apparatus as defined in claim 3 wherein said counting means is a count-down binary counter connected to receive a scaled length and to receive said clock pulses for counting down said scaled length to zero, thereby counting a number of said clock pulses proportional to the specified length of a graphic line to be displayed.

5. Apparatus as defined in claim 4 wherein said digital means for deflection of said electron beam of said tube in said X and Y axes is comprised of separate X and Y binary counters and means for producing X and Y trains of pulses effectively at the respective rates R sin 0 and R cos 0, where R is the scaled length of the line specified and 0 is said specified angle of said line, and wherein said X and Y pulse trains are applied to the least significant binary stages of said X and Y counters respectively, whereby upon accummulating said trains of pulses in said X and Y counters until said counting means counts down to zero in response to clock pulses, at a fixed frequency, the electron beam is deflected said distance R at said angle 0 without changing the connections of the pulse trains to the least significant binary stages of said X and Y counters for scaling, thereby maintaining a substantially constant beam deflection rate for lines displayed at any selected scale. 

1. In a cathode-ray tube display system having digital means for deflection of an electron beam in said tube, said digital deflection means including means for storing a number proportional to the length of a graphic line to be displayed and means for counting a number of fixed-frequency clock pulses equal to said stored number to control said deflection means in displaying a graphic line, an improvement comprised of means for scaling said stored number for a desired graphic display scale by shifting said stored number in said storage means, thereby altering the number of clock pulses counted for the graphic line displayed to alter the scale thereof while maintaining the deflection rate of said beam constant for all range scales, thereby maintaining uniform brightness in the display of graphic lines of all lengths at all scales.
 2. In a cathode-ray tube display system for displaying graphic lines, said system having digital means for deflection of an electron beam in said tube in an X axis direction and digital means for simultaneous deflection of said electron beam in a Y axis direction while displaying a graphic line of a specified length at a specified angle with respect to one of said axes, said x- and y-axis deflection means including a source of clock pulses occurring at a fixed rate and means for counting a number of said clock pulses proportional to the specified length of a graphic line to be displayed in order to produce a running line length count for the graphic line specified, an improvement comprised of means for storing said length of a line to be displayed in binary digital form, and means for scaling said length for a desired graphic display scale before counting clock pulses by shifting said length in said storing means, thus altering the numBer of clock pulses counted to alter the scaled length of the graphic line displayed while maintaining the deflection rate of said beam constant for uniform brightness.
 3. Apparatus as defined in claim 2 wherein said scaling means is comprised of a shift register and said scaling means is comprised of means for applying shift pulses to said shift register, one shift pulse for each binary order of difference in the desired scale over a range scale which requires the maximum number of clock pulses to be counted for a line of maximum length.
 4. Apparatus as defined in claim 3 wherein said counting means is a count-down binary counter connected to receive a scaled length and to receive said clock pulses for counting down said scaled length to zero, thereby counting a number of said clock pulses proportional to the specified length of a graphic line to be displayed.
 5. Apparatus as defined in claim 4 wherein said digital means for deflection of said electron beam of said tube in said X and Y axes is comprised of separate X and Y binary counters and means for producing X and Y trains of pulses effectively at the respective rates R sin theta and R cos theta , where R is the scaled length of the line specified and theta is said specified angle of said line, and wherein said X and Y pulse trains are applied to the least significant binary stages of said X and Y counters respectively, whereby upon accummulating said trains of pulses in said X and Y counters until said counting means counts down to zero in response to clock pulses, at a fixed frequency, the electron beam is deflected said distance R at said angle theta without changing the connections of the pulse trains to the least significant binary stages of said X and Y counters for scaling, thereby maintaining a substantially constant beam deflection rate for lines displayed at any selected scale. 